This invention relates to a logic synthesis method for generating a semiconductor integrated circuit from data of register transfer level. This invention particularly pertains to a logic synthesis method for generating a low-power semiconductor integrated circuit and to a low-power semiconductor integrated circuit.
In recent years, a procedure known as a top-down design method has been used to lay out semiconductor integrated circuits. In the top-down design method, a targeted semiconductor integrated circuit is represented using functional descriptions of register transfer level (RTL). The processing of logic synthesis with the aid of RTL functional descriptions is carried out to generate targeted semiconductor integrated circuits.
FIG. 24 shows a usual RTL functional description. FIG. 25 shows a logic circuit, i.e., a semiconductor integrated circuit, which is generated by means of a logic synthesis technique using the FIG. 24 RTL functional description.
The FIG. 24 RTL functional description is one which specifies, at functional level, data transfer between registers. r1, r2, r3, and r4 represent respective registers. func1, func2, func3, and func4 are functional descriptions of combinational logic circuits connected between the registers. "assign" and "always" are sentences describing the connections of the registers with the combinational logic circuits.
When synthesizing a logic with the use of the FIG. 24 RTL functional description, it is determined on an area/rate tradeoff curve by giving area or rate constraint requirements.
In a logic of FIG. 25 generated from the FIG. 24 RTL functional description, 101, 103, 105, and 107 are flip-flops as a result of the mapping of the registers r1, r2, r3, and r4 by means of logic synthesis. The flip-flops 101, 103, 105, and 107 directly correspond to the respective registers r1, r2, r3, and r4. 108 is a clock buffer. 100, 102, 104, and 106 are combinational logic circuits respectively corresponding to func1, func2, func3, and func4 of FIG. 24 RTL functional description. The combinational logic circuits 100, 102, 104, and 106 are circuits that are mapped from the FIG. 24 RTL functional description as a single circuit on an area/rate tradeoff curve.
The power consumption P of the semiconductor integrated circuit can be found by: EQU P=f.times.C.times.V.sup.2
where f is the operating frequency, C the load capacitance, and V the supply voltage. There are three ways of reducing the power consumption of the semiconductor integrated circuit. The first way is to reduce the operating frequency f. The second way is to reduce the load capacitance C. The third way is to reduce the supply voltage V. Of these three ways the third one is considered as the most effective way.
The third way, however, produces the problem that if the supply voltage is set low, this increases the delay time of a critical path that has the maximum delay time among a great many paths together forming a logic circuit.
With a view to providing a solution to the above-described problem, Japanese Patent Application, published under Pub. No. 5-299624, .[.shows a technique. In accordance with this technique,.]. .Iadd.discloses that .Iaddend.logic gates, not required to operate at a high speed, are driven by a low-voltage source, whereas other logic gates, required to operate at a high speed, are driven by a high-voltage source. .[.In other words, this technique is trying to reduce the overall power consumption of the semiconductor integrated circuit by driving only logic gates constituting a critical path using high voltage, without increasing the delay time of the critical path. This technique, however, suffers the following drawbacks..]. .Iadd.However, the foregoing Japanese Patent Application fails to disclose the use of two voltage sources comprising a high and low voltage source in conjunction with any given critical path..Iaddend.
When downloading data from a low-voltage-driven, slow-speed logic gate to a high-voltage-driven, high-speed logic gate, this requires the provision of a level converter between these two logic gates in order that the output of the former logic gate increases in voltage level. Such is shown in Japanese Patent Application, published under Pub. No. 5-67963. Each combinational logic circuit of FIG. 25 is made up of a great many logic gates (see FIGS. 26 and 27). Suppose a critical path is one represented by bold line in the figures. In order to drive such a critical path by a high-voltage source, a level converter must be arranged at points marked with symbol .smallcircle.. In FIG. 26, eight level converters .[.muse.]. .Iadd.must .Iaddend.be placed. In FIG. 27, 12 level converters must be placed. Semiconductor integrated circuits of large-scale integration contain a great number of combinational logic circuits, therefore containing a great number of logic gates. Accordingly, in a semiconductor integrated circuit of large-scale integration, a great number of level converters must be arranged in a single combinational logic circuit with a critical path. Further, there are many combinational logic circuits containing a critical path. This means that the entire semiconductor integrated circuit will have to contain an enormous number of level converters. With respect to a limited number of combinational logic circuits, it is possible to locate where to arrange level converters. However, if the entire semiconductor integrated circuit of large-scale integration is concerned, to locate where to arrange level converters is considerably troublesome and is a time consuming job. Complicated design work is required.